Last time I looked at a simple 16-bit RISC processor aimed at students. It needed a little assist on documentation as well as had a missing file, however I managed to get it to simulate utilizing a free on the internet tool called EDA Playground. This time, I’ll take you with the code details as well as exactly how to run the simulation.
You’ll want to refer to the previous publish if you didn’t checked out it already. The diagrams as well as tables provide a high-level overview that will assist you comprehend the files discussed in this post.
If you wished to really program this on a genuine FPGA, you’d have a little work to do. The memory as well as register initialization is performed in a method that works fine for simulation, however wouldn’t work on a genuine FPGA. Anyway, let’s get started!
File-by-File
If you take each data individually, none of them are extremely difficult to understand. Here’s a quick rundown (I’m utilizing the data names I’ll utilize in my on the internet simulation):
Parameter.v – This is like an include data that sets some fundamental definitions for every other file.
prog.v – This is the direction memory. A simple module, it takes an address as well as presents data for that address. The $readmemb directive reads the data from a data (test.prog).
register.v – The register file. This is almost like the direction memory however it has two checked out ports as well as you can compose to it.
data.v – The RAM memory. This is almost like the registers, however larger as well as with a single checked out port. There is some simulation code that opens a data as well as prints the memory comments, however I deleted that as it was just for debugging. The preliminary content comes from the test.data file.
alu.v – You’d believe this would be complicated, however it isn’t. It just takes two inputs as well as does something to produce the output. Something simple like adds or subtracts. The always @(*) tells Verilog not to produce clocked logic for this. It just turns into some simple gates as well as muxes.
Datapath_Unit.v – This is one of the more complex files, although if you dig into it, you’ll see it is mainly bulk. This data produces all the resources (like the registers as well as memories) as well as wires them together.
Control_Unit.v – one more longer module, this just implements the direction table, setting the control lines based on the present instruction.
ALUControl.v – This data decodes instructions for the ALU. It was missing on the original post. Oddly, there is one more similar CPU on the exact same site that has an ALUControl file, however it is clearly for a different direction set. However, starting keeping that data as well as utilizing the style table, I was able to recreate it. If [fpga4students] corrects this, the files may look extremely different.
design.sv – This data is required for the EDAPlayground simulator I’m using. It contains the top-level elements (the data path as well as the control unit). since EDAPlayground only processes this file, it is necessary for it to include the other files mentioned above. This causes some warnings since each of them has a timescale directive, however this is harmless.
testbench.sv – The testbench isn’t part of the genuine design, however just sets up the simulation as well as collects results. I had to modify it a bit to work with EDAPlayground, however the operation is the same. It just produces a CPU, feeds it a clock, as well as lets it run for a while. The test program as well as memory contents are in test.prog as well as test.data.
Simulation
You can do one of two things. You can open up my copy of the style ready-to-go, however that may not be your finest option. I’d suggest you just go to EDAPlayground and produce a new Verilog project. then begin moving the files over from the original post. You’ll run into errors as well as missing files. See exactly how many you can fix. If you get stumped, then you can utilize my copy to assist you if you get stumped. You’ll discover more that way.
If you do choose to try it, right here are a few tips about EDAPlayground. You don’t requirement UVM/OVM selected, nor do you requirement any type of other libraries. I utilized Icarus Verilog 0.9.7, however you might most likely utilize any type of of the Verilog tools available. You do want to inspect the EPWave checkbox as well as you’ll requirement to add this to the inital part of testbench:
initial
začať
$dumpfile(“dump.vcd”);
$dumpvars;
Use the + indication next to the data name tabs to make new files. EDAPlayground has a limit of ten files per pane. Remember, you’ll have to include any type of .v files you produce in either testbench.sv or design.sv. You don’t requirement to include the data files since the other files utilize them indirectly.
Run!
Once you have all the errors worked out, you can press Run as well as you’ll get the waveform viewer, EPWave. You have Ak chcete pridať signály záujmu, takže môžete sledovať CPU pri práci. Bolo by zábavné pridať nejaké I / O zariadenia v pamäti alebo niektorých ladenie portov, takže by ste mohli sledovať veci o niečo lepšie. Zvyčajne sa pozerám na programový pult, ako aj register komponáže prístav, aby ste získali koncepciu toho, čo sa deje vo vnútri.
Pôvodný kód mal program, ktorý vykonal veľké pokyny. Vyjadril som to, rovnako ako ho nahradil:
0000_0100_0000_0000 // 0000: tony R0 <- MEM (R2 + 0) od R2 = 0 TOTO VYKONÁVANÍ 1 V R0 0000_0100_0100_0000 // 0002: Tons Presné rovnaké v R1 (R1 bude vždy obsahovať 1) // miesto 8 (bajt), 4 (slovo): 0010_0000_0101_0000 // 0004: R2 = R0 + R1 0001_0010_1000_0000 // 0006: MEM [R1] = R2 (to je MEM [1] = R2 0000_0010_0000_0000 // 0008: R0 = MEM [R1] 1101_0000_0000_0011 // 000A: Skok na miesto # 4 (CPU sa vynásobí 2, ako aj pridať 2) // žiadny smer na 000c, avšak PC tam bude visieť, zatiaľ čo to spracováva skok Mali by ste byť schopní dodržiavať prírastkovú hodnotu, ktorá sa skladá do pamäte, rovnako ako sledovať protikladový cyklus späť na miesto 4 s každou slučkou. Tu je typická relácia: Vynechal som veľa interiérových signálov, ale môžete vidieť, že pamäťová adresa 1 je nastavená na 2, ako aj potom na 3 na prvých dvoch iteráciách slučky. Koniec hry Je to skvelá akademická CPU? Nie som si istý. Niektoré jednoduchšie CPU existujú, ale sú často málo, pretože sú zložité alebo sú mimoriadne nepraktické. Čokoľvek viac náročné, než je to s najväčšou pravdepodobnosťou tak dobre, aby ste si prečistili pre začiatočníkov. Zatiaľ čo verím, že by ste mali mať nejaké pochopenie základného Verilogu skôr, ako budete mať niečo podobné, dokumentácia bola trochu riedka (a mätúci) v niektorých oblastiach. Je zrejmé, že to bolo skvelé dostačujúce, pretože som to fungoval, avšak, ak práve začínate, s najväčšou pravdepodobnosťou by ste ocenili trochu viac pomoci, ako aj vysvetlenia. Máte preferovaný akademický verilog CPU? Stále hľadám, že osoba, ktorá je "práve pravda".